Description[ edit ] Features and performance[ edit ] The series was generally intended for embedded systems , as microcontrollers with external memory. Therefore, to reduce the number of integrated circuits required, it included features such as clock generator , interrupt controller , timers , wait state generator, DMA channels, and external chip select lines. Multiply and divide also showed great improvement being several times as fast as on the original and multi-bit shifts were done almost four times as quickly as in the A useful immediate mode was added for the push, imul, and multi-bit shift instructions. These instructions were also included in the contemporary and in successor chips.
|Published (Last):||24 January 2016|
|PDF File Size:||4.96 Mb|
|ePub File Size:||12.77 Mb|
|Price:||Free* [*Free Regsitration Required]|
Execution Unit Memory Management Unit As we have already discussed that the possess the ability of 3 stage pipelining thus performs fetching, decoding and execution simultaneously along with memory management and bus accessing. Thus all these units operate parallely. This pipelining technique leads to reduction in overall processing time thereby increasing the performance of the overall system.
Let us now move further and understand the operation of each unit in detail. Whenever a need for an instruction or a data fetch is generated by the system then the BIU generates signals according to the priority for activating the data and address bus in order to fetch the data from the desired address. The BIU connects the peripheral devices through the memory unit and also controls the interfacing of external buses with the coprocessors.
Code Prefetch Unit This unit fetches the instructions stored in the memory by making use of system buses. Whenever the system generates a need for an instruction then the code prefetch unit fetches that instruction from the memory and stores it in byte prefetch queue.
So to speed up the operation this unit fetches the instructions in advance and the queue stores these instructions. The sequence in which the instructions are fetched and gets stored in the queue depends on the order they exist in the memory. As this unit fetches one double word in single access. So, in such a case, it is not necessary that each time only a single instruction will be fetched, as the fetched instruction can be parts of two different instructions.
It is to be noted here that, code prefetching holds lower priority than data transferring. As whenever, a need for data transfer is generated by the system then immediately the code prefetcher leaves the control over the buses. So that the BIU can transfer the required data. But prefetching of instruction and storing it in the queue reduces the wait for the upcoming instruction to almost zero. Instruction Decode Unit We know that instructions in the memory are stored in the form of bits.
So, this unit decodes the instructions stored in the prefetch queue. Basically the decoder changes the machine language code into assembly language and transfers it to the processor for further execution. Execution Unit The decoded instructions are stored in the decoded instruction queue. So, these instructions are provided to the execution unit in order to execute the instructions. The execution unit controls the execution of the decoded instructions. This unit has a bit ALU, that performs the operation over bit data in one cycle.
Also, it consists of 8 general purpose as well as 8 special purpose registers. These are used for data handling and calculation of offset address. Memory Management Unit This unit has two separate units within it. These are Segmentation Unit and Paging Unit Segmentation unit: The segmentation unit plays a vital role in the microprocessor.
It offers protection mechanism in order to protect the code or data present in the memory from application programs. It gives 4 level protection to the data or code present in the memory. Every information in the memory is assigned a privilege level from PL0 to PL3. Here, PL0 holds the highest priority and PL3 holds the lowest priority. Suppose a file either data or code is needed to be accessed is stored in the memory at PL0.
Then only those programs which are working at PL0 would be able to access that file. While other programs will not be able to access the same. As PL0 has higher priority than PL1. Providing protection to the data or code inside the system is the most advantageous factor that was first given by microprocessor.
Paging Unit: The paging unit operates only in protected mode and it changes the linear address into physical address. As the programmer only provides the virtual address and not the physical address.
The segmentation unit controls the action of paging unit, as the segmentation unit has the ability to convert logical address into linear address at the time of executing an instruction. Basically it changes the overall task map into pages and each page has a size of 4K.
This allows the handling of task in the form of pages rather than segments. Paging unit supports multitasking. This is so because the physical memory is not required to hold the whole segment of any task. Despite, only that part of the segment which is needed to be currently executed must be stored in that memory whose physical address is calculated by the paging unit. This resultantly reduces the memory requirement and hence this frees the memory for other tasks. Thus by this we get an effective way for managing the memory to support multitasking.
This is all about the architecture of microprocessor. A noteworthy point over here is that has 2 different versions. These are SX and DX. The SX stands for single execution while the DX stands for double execution. While DX has a data bus of bit. Whenever we talk about then it nothing but DX having bit data bus.
But sometimes a system having microprocessor needs to improve the its performance as well as protection. And we know that is a bit microprocessor, that operates on 2 banks. But in general has a bit data bus that needs 4 banks.
So, to access some of the features of in a system having processor, we use SX as processor having data bus of bit. Thus in this case, a system can be upgraded to facilities of by simply changing the processor despite changing the overall system. This is reason why we have SX version of the microprocessor.
Generally, we consider as DX, a processor with bit of data bus. You Might Also Like:.
Execution Unit Memory Management Unit As we have already discussed that the possess the ability of 3 stage pipelining thus performs fetching, decoding and execution simultaneously along with memory management and bus accessing. Thus all these units operate parallely. This pipelining technique leads to reduction in overall processing time thereby increasing the performance of the overall system. Let us now move further and understand the operation of each unit in detail. Whenever a need for an instruction or a data fetch is generated by the system then the BIU generates signals according to the priority for activating the data and address bus in order to fetch the data from the desired address. The BIU connects the peripheral devices through the memory unit and also controls the interfacing of external buses with the coprocessors.
It has non-multiplexed data and address bus. The size of data bus is bit whereas the size of address bus is bit. It was invented in February by Intel. Further in , Intel produced upgraded version of which was a bit microprocessor. Now the question arises what are the factors that make more advantageous than microprocessor?
Microprocessor - 8086 Overview