They are specifically designed for Off—Line and dc—to—dc converter applications offering the designer a cost—effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle—by—cycle current limiting, programmable output deadtime, and a latch for single pulse metering. These devices are available in an 8—pin dual—in—line and surface mount SO—8 plastic package as well as the 14—pin plastic surface mount SO— The SO—14 package has separate power and ground pins for the totem pole output stage. X indicates either a 2 or 3 to define specific device part numbers.
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They are specifically designed for Off—Line and dc—to—dc converter applications offering the designer a cost—effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle—by—cycle current limiting, programmable output deadtime, and a latch for single pulse metering. These devices are available in an 8—pin dual—in—line and surface mount SO—8 plastic package as well as the 14—pin plastic surface mount SO— The SO—14 package has separate power and ground pins for the totem pole output stage.
X indicates either a 2 or 3 to define specific device part numbers. Motorola, Inc. Maximum Package power dissipation limits must be observed. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. V Output Compensation 5. Comparator gain is defined as: AV? Output Deadtime versus Oscillator Frequency 1.
Oscillator Discharge Current versus Temperature 9. Reference Voltage Change versus Source Current? This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction.
Operation to kHz is possible. This pin is the combined control circuitry and power ground. Peak currents up to 1. This pin is the positive supply of the control IC.
This is the reference output. It provides charging current for capacitor CT through resistor RT. This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. The Output high state VOH is set by the voltage applied to this pin.
With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This pin is the control circuitry ground return and is connected back to the power source ground. No connection. These pins are not internally connected. A representative block diagram is shown in Figure Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.
During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency.
These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 3 and 4. In many noise—sensitive applications it may be desirable to frequency—lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the circuit shown in Figure A method for multi—unit synchronization is shown in Figure By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved. Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided.
It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1. The non—inverting input is internally biased at 2. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is —2. A which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. This guarantees that no drive pulses appear at the Output Pin 6 when pin 1 is at its lowest state VOL.
This occurs when the power supply is operating and the load is removed, or at the beginning of a soft—start interval Figures 23, Thus the error signal controls the peak inductor current on a cycle—by—cycle basis. The inductor current is converted to a voltage by inserting the ground—referenced sense resistor RS in series with the source of output switch Q1. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: V — 1.
Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1. A simple method to adjust this voltage is shown in Figure The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk max clamp voltage.
A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability refer to Figure Pin numbers in parenthesis are for the D suffix SO—14 package.
The positive power supply terminal VCC and the reference output Vref are each monitored by separate comparators. Each has built—in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The Vref comparator upper and lower thresholds are 3. The large hysteresis and low startup current of the UCXB makes it ideally suited in off—line converter applications where efficient bootstrap startup techniques are required Figure The UCXB is intended for lower voltage dc—to—dc converter applications.
A 36 V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active.
This characteristic eliminates the need for an external pull—down resistor. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk max clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC.
Reference The 5. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short— circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire—wrap or plug—in prototype boards.
High frequency circuit layout techniques are imperative to prevent pulse—width jitter. This is usually caused by excessive noise pick—up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low—current signal and high—current switch and output grounds returning on separate paths back to the input filter capacitor.
Ceramic bypass capacitors 0. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as 10 possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise—generating components.
Figure 19A shows the phenomenon graphically. At t0, switch conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at a slope of m2, until the next oscillator cycle. The unstable condition can be shown if a perturbation is added to the control voltage, resulting in a small?
I dashed line. With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn—on t2 is increased by? The minimum current at the next cycle t3 decreases to? Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. Figure 19B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the?
I perturbation will decrease to zero on succeeding cycles.
UC3842BN, Токовый ШИМ-контроллер [PDIP-8]
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